Search - frequency divider

[VHDL-FPGA-Verilog] half_integer

Description: 数控分频器：以2.5分频为例的半整数分频器-half-integer frequency divider
Platform: | Size: 212992 | Author: litong | Hits:

[Other] divider8

Description: 使用硬件描述语言设计8分频器，并将结果通过七段数码管显示-The hardware description language is used to design the 8-frequency divider, and the result is displayed by 7-segment LED
Platform: | Size: 1500160 | Author: 王锋 | Hits:

[VHDL-FPGA-Verilog] fenpin5

Description: 五分频器的VHDL语言设计，改变相关参数，可得到其他分频器，便于学习VHDL语言-Five frequency divider VHDL language design, change the relevant parameters, you can get other dividers, easy to learn VHDL language
Platform: | Size: 108544 | Author: XINGJINGYU | Hits:

[Software Engineering] DDS

Description: 分频器，利用quartus软件或者modelsim软件对频率进行分频，也可在硬件上观察出对信号的分频-Frequency divider, quartus software or modelsim software is used to analyse the frequency divider, can also be used on hardware to detect the signal frequency division
Platform: | Size: 1024 | Author: 梁晴 | Hits:

[VHDL-FPGA-Verilog] Example5

Description: 数控分频器设计数控分频器的功能就是当输入端给定不同的输入数据时，分频器对输入时钟信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器来设计完成的，方法是将计数溢出位与预置数装载信号相接得到-NC NC divider divider design feature is that when the given input different input data, the frequency divider with a different frequency division ratio of the input clock signal, the count value NC divider is parallel preset adding counter to the design is completed, the method is to count the number of overflow bit load signal with a preset phase to give
Platform: | Size: 3072 | Author: 贺泽伟 | Hits:

[VHDL-FPGA-Verilog] Freq_gen

Description: XILINX 分频器 100MHz，1KHz， 1Hz(XILINX frequency divider 100MHz, 1KHz, 1Hz)
Platform: | Size: 1014784 | Author: hush_puppy | Hits:

[VHDL-FPGA-Verilog] 7_1

Description: 电路端口为：异步清零输入端口rst，输入时钟clk_in，输出时钟clk_out。并分别采用两种以上的方法实现。(Frequency divider circuit port is: Asynchronous Clear input port rst, input clock clk_in, output clock clk_out. And use two or more methods to achieve.)
Platform: | Size: 271360 | Author: 白学 | Hits:

[VHDL-FPGA-Verilog] verilog_PLL

Description: 全数字锁相环的verilog源代码，包括鉴相器，K变摸可逆计数器，加减脉冲器和N分频器。已经仿真实现。(All digital phase-locked loop Verilog source code, including phase discriminator, K variable touch reversible counter, add and subtract pulse and N frequency divider. Have been implemented by simulation.)
Platform: | Size: 11264 | Author: 小米1 | Hits:

[VHDL-FPGA-Verilog] FPGA_test_20170620_1

Description: 对50M的系统时钟进行分频处理，然后控制led的闪灭(Frequency divider controls led.)
Platform: | Size: 7491584 | Author: 何谓因你心醉 | Hits:

[Other] AD9512_SPI_Config

Description: 用户可以通过各分频器改变一路时钟输出相对于其它时钟输出的相位，这种相位选择功能可用于时序粗调。(The user can change the clock all the way through the frequency divider output relative to other clock output phase, the phase selection function can be used for timing coarse adjustment.)
Platform: | Size: 1024 | Author: 小黄a小黄蛋 | Hits:

[VHDL-FPGA-Verilog] fenpin51

Description: 任意整数分频器，输出方波可调占空比（已仿真下板子验证）第一个系数为分频系数，第二个为高电平所占整个方波的比例(Arbitrary integer frequency divider, output square wave adjustable duty cycle (has been simulated under board verification), the first factor for the frequency division coefficient, the second for the high level, the proportion of the whole square wave)
Platform: | Size: 63488 | Author: 奋斗小二逼 | Hits:

[VHDL-FPGA-Verilog] uart_rxd

Description: 用Verilog实现UART，有分频模块，可调整波特率(UART with Verilog, there are frequency divider module, can adjust the baud rate)
Platform: | Size: 10801152 | Author: zmxer | Hits:

[Other] guan 27

Description: 分频器分频为2Hz后，使计数时间变为0.5秒一个，将此时的频率传给计数器，计数器计数的变化时间就变为0.5秒一变然后再用数码管显示出数字的变化，即可得到一个从0~9变化的计时器。文件名为随便起的项目名称，使用时如果更改需要和代码中的实体名等一起更改(Frequency divider for 2Hz, the counting time is 0.5 seconds a, the frequency to change the time counter counter becomes 0.5 seconds for a variable and then use the digital display changes, you can get a change from the 0~9 timer. The file name is the name of the item that you want to change when used, and the changes need to be changed together with the entity name in the code)
Platform: | Size: 193536 | Author: 关关关 | Hits:

[VHDL-FPGA-Verilog] fen

Description: 分频器,可以实现时钟分频，频率变小则周期变长(Frequency divider, can realize clock frequency division, frequency becomes smaller, then the cycle becomes longer)
Platform: | Size: 140288 | Author: 佳12345 | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: 用verilog语言设计了一个分频器，晶振频率为50MHz(A frequency divider is designed in Verilog language. The frequency of crystal oscillator is 50MHz)
Platform: | Size: 4245504 | Author: vsslms | Hits:

[VHDL-FPGA-Verilog] oneMHZ

Description: VHDL语言编写的20Mhz分频器，时间为1秒(20Mhz frequency divider)
Platform: | Size: 191488 | Author: zuys | Hits:

[Embeded-SCM Develop] wannianli

Description: 2、掌握QuartusII软件的使用； 3、掌握计数器的设计； 4、掌握分频器的设计； 5、掌握时、分、秒的设计； 6、数码管的扫描显示； 7、掌握数字钟的整体设计(2, master the use of QuartusII software; 3. Master the design of the counter; 4. Master the design of frequency divider; 5, mastering the design of time, time and time. 6, the scanning display of the digital tube; 7. Master the overall design of the digital clock)
Platform: | Size: 2040832 | Author: 夜光 | Hits:

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